The present embodiments relate to electronic circuit devices and are more particularly directed to a hold time latch with reduced voltage leakage at its output precharge node.
Electronic circuits have become prevalent in numerous applications, including uses for devices in personal, business, and other environments. Demands of the marketplace affect many aspects of circuit design, including factors such as device power consumption and speed. Various electronic circuits now implement what is known in the art as dynamic, or domino, logic. Dynamic logic circuitry operates in two phases, a precharge phase during which various precharge nodes are precharged to a first voltage, and an evaluate phase during which the data is read based on the voltage at the precharge node, where the precharge voltage therefore may be read as a first logic state if undisturbed or where that precharge voltage may be first discharged and then read as a second logic state that is complimentary to the first logic state. Further, dynamic logic often passes signals through two or more stages, so that an evaluation by a first stage that discharges the first stage precharge node results in an output to the input of a second stage, and where that signal also thereby triggers a discharge of a precharge node in the second stage. In this manner, a number of stages may be triggered as the evaluate phases of the stages overlap and the output of each stage propagates through to the next successive stage.
In one type of dynamic logic, the signals pass from one stage having a first control clock to a second stage having a delayed second clock. In these circuits, there is a designed overlap between the first and second clocks so that the second stage is in its evaluate phase long enough to be triggered by the output of the first stage, yet the first stage returns to its precharge phase while the second stage thereafter for some period of time remains in its evaluate phase. It is during the time that the first stage output remains valid, known as the hold time, that the subsequent stage is typically able to trigger (i.e., evaluate) based on then-valid data from the first stage. As a result, such a circuit is often referred to as a hold time latch. Consequently, data may propagate through this as well as similar connections without the need for complicated additional latching circuitry. Once the first stage returns to its precharge phase, however, the output it provides to the second stage is no longer valid, since that output is then subject to the precharge operation of the first stage. Accordingly, it is also known in the art to include feedback transistors, also referred to as keeper transistors, connected to the output of the second stage in order to maintain its output state steady during the time when the first stage returns to its precharge phase. The feedback arises in that each keeper transistor has its gate controlled by the second stage output and is coupled to provide a maintenance voltage at the precharge node of the second stage. More particularly, often both a p-channel transistor and an n-channel transistor are connected as keeper transistors, where if the second stage output is low then the keeper p-channel transistor is enabled to keep a high voltage at the second stage precharge node, while if the second stage output is high then the keeper n-channel transistor is enabled to keep a low voltage at the second stage precharge node.
By way of further background, it has heretofore been recognized that current may leak from the second stage precharge node during its evaluate phase in the instance when the first stage provides, or was providing, a low output during the evaluate phase of the first stage. Specifically, under these conditions, the discharge path of the second stage is not enabled due to the low output of the first stage; however, current may leak through the second stage disabled transistor that is receiving the low data output from the first stage. Indeed, it is known in the art that the particular second stage data-receiving transistor may be a so-called low threshold voltage (“LVT”) transistor, where such transistors are sometimes used in a discharge path in order to increase the speed of that path when the path is enabled. In such a case, each LVT transistor has a relatively lower threshold transistor as compared to other transistors in the same circuit, and such other transistors are therefore referred to as high threshold voltage (“HVT”) transistors. Indeed, for numerous additional details relating to such an approach and related aspects, the reader is invited to review U.S. Pat. No. 5,831,451, entitled “Dynamic Logic Circuits Using Transistors Having Differing Threshold Voltages,” issued Nov. 3, 1998, having the same inventor and assignee of the subject application, and U.S. Pat. No. 5,821,778, entitled “Using Cascode Transistors Having Low Threshold Voltages,” issued Oct. 13, 1998, having the same inventor and assignee of the subject application, where both of these two patents are hereby incorporated herein by reference. In any event, the use of an LVT transistor correspondingly provides increased leakage when it is not enabled and, as such, when implemented in the discharge path of a hold time latch, that transistor increases leakage when that discharge path is not enabled. Increased leakage is undesirable because it increases device power consumption and, indeed, if severe, may jeopardize the proper operation of the hold time latch.
While the preceding approaches implemented with respect to hold-time latches have proven satisfactory in many applications, the leakage in the discharge path of the second stage may be unacceptable, particularly when the leakage in that path is increased due to the use in the path of one or more LVT n-channel transistors. Further, while the p-channel keeper transistor may provide some current to compensate for the leakage of an LVT n-channel transistor in the second stage discharge path, it has been recognized in connection with the preferred embodiments that such an approach alone may not be satisfactory for various reasons. Specifically, in order for the p-channel keeper transistor to serve its purpose in this regard, the current it provides when enabled (i.e., the “on-current” of the p-channel transistor) must be sufficiently larger than the leakage current of the LVT n-channel transistor (i.e., the “off-current” of the n-channel transistor). However, this goal is becoming increasingly more difficult because there are various factors that are tending to decrease the ratio of the on-current of the HVT p-channel transistor relative to the off-current of the LVT n-channel transistor. For example, as the system source voltage, VDD, decreases in circuit design as is the current trend, the above-described current ratio decreases. As another factor, transistor threshold voltage is a function of temperature, that is, high temperatures decreases threshold voltage, and this too decreases the subject current ratio. As still another factor, there is a trend to build many low threshold voltage transistors in a manner to provide more drive current, once more decreasing the above-discussed ratio. Finally, n-channel transistors are stronger in current provision than p-channel transistors, still again decreasing the above-discussed ratio. With these factors, note therefore that the HVT p-channel transistor attempts to source sufficient current to compensate for the leakage of the LVT n-channel transistor, but in that attempt an increasingly larger amount of voltage is dropped across the HVT p-channel transistor, particularly in a relative sense as its strength is reduced relative to that of the n-channel transistor. The increase in voltage drop may be detrimental for various reasons, including calling into question the reliability of data validity of the hold time latch.
Given the preceding, the preferred embodiments seek to improve upon the limitations and drawbacks of the prior art, as discussed in detail below.